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1 100v, 2a peak, high frequency half-bridge drivers with rising edge delay timer HIP2122, hip2123 the HIP2122 and hip2123 are 100v , high frequency, half-bridge mosfet driver ics. they are ba sed on the popular isl2100a and isl2101a half-bridge drivers. like the isl2100a, two logic inputs, li and hi, control both bridge outputs, lo and ho. all logic inputs are v dd tolerant. these drivers have a programmable dead-time to insure break-before-make operation between the high-side and low-side drivers. the dead-time is adjustable up to 220ns. the internal logic does not prevent both outputs from turning on simultaneously if both inputs ar e high simultaneously for a time greater than the programmed delay. a single pwm logic input controls both bridge outputs (ho, lo). an enable pin (en), when low, drives both outputs to a low state. all logic inputs are v dd tolerant and the HIP2122 has cmos inputs with hysteresis for superior operation in noisy environments. the HIP2122 has hysteretic inputs with thresholds that are proportional to v dd . the hip2123 has 3.3v logic/ttl compatible inputs. two package options are provided . the 10 lead 4x4 dfn package has standard pinouts. the 9 lead 4x4 dfn package omits pin 2 to comply with 100v conductor spacing per ipc-2221. features ? 9 ld tdfn ?b? package compliant with 100v conductor spacing guidelines per ipc-2221 ? break-before-make dead-time prevents shoot-through and is adjustable up to 220ns ? bootstrap supply max voltage to 114vdc ? wide supply voltage range (8v to 14v) ? supply undervoltage protection ? cmos compatible input thresholds with hysteresis (HIP2122) ?1.6 /1 typical output pull-up/pull-down resistance ?on-chip 1 ? bootstrap diode applications ? telecom half-bridge dc/dc converters ?ups and inverters ?motor drives ? class-d amplifiers ? forward converter with active clamp related literature ? fn7668 , hip2120, hip2121 ?100v, 2a peak, high frequency half-bridge drivers with adjustable dead time control and pwm input? figure 1. typical application figure 2. dead-time vs timing resistor vdd hb ho hs lo vss hi li 100v max rdt feedback with isolation pwm controller secondary circuits HIP2122, hip2123 epad half bridge 200 160 140 120 100 80 60 40 20 deadtime (ns) rdt (k ? ) 81624324048566480 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. december 23, 2011 fn7670.0
HIP2122, hip2123 2 fn7670.0 december 23, 2011 block diagram pin configurations HIP2122, hip2123 (10 ld 4x4 tdfn) top view HIP2122, hip2123 (9 ld 4x4 tdfn) top view level shift under voltage under voltage epad delay HIP2122, hip2123 HIP2122 HIP2122 HIP2122/23 HIP2122/23 optional inversion for future part numbers vdd ho rdt lo hb ho hs lo vss delay epad is electrically isolated epad 1 2 3 4 5 10 9 8 7 6 vdd hb ho hs nc lo vss li hi rdt epad 1 3 4 5 10 9 8 7 6 vdd hb ho hs lo vss li hi rdt
HIP2122, hip2123 3 fn7670.0 december 23, 2011 pin descriptions 9 ld tdfn 10 ld tdfn symbol description 1 1 vdd positive supply voltage for lower gate driver. decouple this pin with a ceramic capacitor to vss. 3 2 hb high-side bootstrap supply voltage referenced to hs. connec t the positive side of bootstrap capacitor to this pin. bootstrap diode is on-chip. 4 3 ho high-side output. connect to gate of high-side power mosfet. 5 4 hs high-side source connection. connect to source of high-side power mosfet. connect the negative side of bootstrap capacitor to this pin. 8 8 li low side driver input. for li = 1, lo = 1 after programmed delay time; for li = 0, lo = 0 with minimal delay. 7 7 hi high side driver input. for hi = 1, ho = 1 after pr ogrammed delay time; for hi = 0, ho = 0 with minimal delay. 9 9 vss negative supply input, which will generally be ground. 10 10 lo low-side output. connect to gate of low-side power mosfet. - 5 nc no connect. this pin is isolated from all other pins. 6 6 rdt a resistor connected between this pin and vss adds addi tional delay time to the normal rising edge propagation delay. - - epad exposed pad. connect to ground or float. the epad is electrically isolated from all other pins. ordering information part number (notes 1, 2, 4) part marking input temp. range (c) package (pb-free) pkg. dwg. # HIP2122frtaz hip 2122az cmos - 40 to +125 10 ld 4x4 tdfn l10.4x4 hip2123frtaz hip 2123az 3.3v/ttl - 40 to +125 10 ld 4x4 tdfn l10.4x4 HIP2122frtbz (note 3) hip 2122bz cmos - 40 to +125 9 ld 4x4 tdfn l9.4x4 hip2123frtbz (note 3) hip 2123bz 3.3v/ttl - 40 to +125 9 ld 4x4 tdfn l9.4x4 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pbhfree products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. ?b? package option has alternate pin assignments for compliance with 100v conductor spacing guidelines per ipc-2221. note tha t pin 2 is omitted for additional spacing. 4. for moisture sensitivity level (msl), please see device information page for HIP2122 , hip2123 . for more information on msl please see tech brief tb363 .
HIP2122, hip2123 4 fn7670.0 december 23, 2011 table of contents absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 esd ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 switching specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 selecting the boot capacitor value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 transients on hs node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pc board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 epad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
HIP2122, hip2123 5 fn7670.0 december 23, 2011 absolute maximum rating s thermal information supply voltage, v dd , v hb - v hs (notes 5, 6) . . . . . . . . . . . . . . . -0.3v to 18v li and hi input voltage (note 6) . . . . . . . . . . . . . . . . . . .-0.3v to vdd + 0.3v voltage on lo (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to vdd + 0.3v voltage on ho (note 6) . . . . . . . . . . . . . . . . . . . . . vhs - 0.3v to vhb + 0.3v voltage on hs (continuous) (note 6) . . . . . . . . . . . . . . . . . . . . . -1v to 110v voltage on hb (note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118v average current in v dd to hb diode . . . . . . . . . . . . . . . . . . . . . . . . . 100ma maximum recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v to 14v voltage on hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 100v voltage on hs . . . . . . . . . . . . . . . . . . . . . .(repetitive transient) -5v to 105v voltage on hb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v hs + 8v to v hs + 14v and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd - 1v to v dd + 100v hs slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50v/ns thermal resistance (typical) ja (c/w) jc (c/w) 10 ld tdfn (notes 7, 8) . . . . . . . . . . . . . . . 42 4 9 ld tdfn (notes 7, 8) . . . . . . . . . . . . . . . . 42 4 max power dissipation at +25c in free air 10 ld tdfn (notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0w 9 ld tdfn (notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1w storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp esd ratings human body model class 2 (tested per jesd22-a114e). . . . . . . . . . 3000v machine model class b (tested per jesd22-a115-a). . . . . . . . . . . . . . 300v charged device model class iv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. the HIP2122 and hip2123 are capable of derated operation at supply voltages exceeding 14v. figure 20 shows the high-side volt age derating curve for this mode of operation. 6. all voltages referenced to v ss unless otherwise specified. 7. ja is measured in free air with the componen t mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 8. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, r dt = 0 k , pwm= 0v, no load on lo or ho, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. parameters symbol test conditions t a = +25c t a = -40c to +125c units min typ max min (note 9) max (note 9) supply currents v dd quiescent current i dd80 r dt = 80k - 470 850 - 900 a i dd8k r dt = 8k - 1.0 2.1 - 2.2 ma v dd operating current i ddo80k f = 500khz, r dt = 80k - 2.5 3 - 3 ma i ddo8k f = 500khz, r dt = 8k - 3.4 4 - 4 ma total hb quiescent current i hb li = hi = 0v - 65 115 - 150 a total hb operating current i hbo f = 500khz - 2.0 2.5 - 3 ma hb to v ss current, quiescent i hbs li = hi = 0v; v hb = v hs = 114v - 0.05 1.5 - 10 a hb to v ss current, operating i hbso f = 500khz; v hb = v hs = 114v - 1.2 1.5 - 1.6 ma input pins low level input voltage threshold v il HIP2122 (cmos) 3.7 4.4 - 2.7 - v low level input voltage threshold v il hip2123 (3.3v/ttl) 1.4 1.8 - 1.2 - v high level input voltage threshold v ih HIP2122 (cmos) - 6.54 7.93 5.3 8.2 v high level input voltage threshold v ih hip2123 ((3.3v/ttl) - 1.8 2.2 -2.4 v
HIP2122, hip2123 6 fn7670.0 december 23, 2011 input voltage hysteresis v ihys HIP2122 (cmos) - 2.2 - -- v input pull-down resistance r i -210- 100 500 k undervoltage protection v dd rising threshold v ddr 6.8 7.3 7.8 6.5 8.1 v v dd threshold hysteresis v ddh -0.6- -- v hb rising threshold v hbr 6.2 6.9 7.5 5.9 7.8 v hb threshold hysteresis v hbh -0.6- -- v bootstrap diode low current forward voltage v dl i vdd-hb = 100ma - 0.6 0.7 -0.8 v high current forward voltage v dh i vdd-hb = 100ma - 0.7 0.9 -1 v dynamic resistance r d i vdd-hb = 100ma - 0.8 1 -1.5 lo gate driver low level output voltage v oll i lo = 100ma - 0.25 0.4 -0.5 v high level output voltage v ohl i lo = -100ma, v ohl = v dd - v lo - 0.25 0.4 -0.5 v peak pull-up current i ohl v lo = 0v - 2 - -- a peak pull-down current i oll v lo = 12v - 2 - -- a ho gate driver low level output voltage v olh i ho = 100ma - 0.25 0.4 -0.5 v high level output voltage v ohh i ho = -100ma, v ohh = v hb - v ho - 0.25 0.4 -0.5 v peak pull-up current i ohh v ho = 0v - 2 - -- a peak pull-down current i olh v ho = 12v - 2 - -- a electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, r dt = 0 k , pwm= 0v, no load on lo or ho, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. parameters symbol test conditions t a = +25c t a = -40c to +125c units min typ max min (note 9) max (note 9)
HIP2122, hip2123 7 fn7670.0 december 23, 2011 timing diagram switching specifications v dd = v hb = 12v, v ss = v hs = 0v, rdt = 0k , no load on lo or ho, unless otherwise specified. parameters (see ?timing diagram?) symbol test conditions t j = +25c t j = -40c to +125c units min type max min (note 9) max (note 9) ho turn-off propagation delay hi falling to ho falling t plho -3250 - 60 ns lo turn-off propagation delay lo falling to lo falling t pllo -3250 - 60 ns minimum dead-time delay (see note 10) ho falling to lo rising t dthlmin r dt = 80k, hi 1 to 0, li 0 to 1 15 35 50 10 60 ns minimum dead-time delay (see note 10) lo falling to ho rising t dtlhmin r dt = 80k li 1 to 0, hi 0 to 1 15 25 50 10 60 ns maximum dead-rising delay (see note 10) ho falling to lo rising t dthlmax r dt = 8k, hi 1 to 0, li 0 to 1 150 220 300 - - ns maximum dead-time delay (see note 10) lo falling to ho rising t dtlhmax r dt = 8k, li 1 to 0, hi 0 to 1 150 220 300 - - ns either output rise/fall time (10% to 90%/90% to 10%) t rc, t fc c l = 1nf - 10 - - - ns either output rise/fall time (3v to 9v/9v to 3v) t r, t f c l = 0.1mf - 0.5 0.6 - 0.8 s bootstrap diode turn-on or turn-off time t bs -10- - - ns notes: 9. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits are establishe d by characterization and are not production tested. 10. dead-time is defined as the period of time between the lo falling and ho rising or between ho falling and lo rising when the li and hi inputs transition simultaneously. hi ho lo en t ph t r 90% 10% t f 90% li 10% t pl t dt t dt t r and t f for lo are not shown for clarity
HIP2122, hip2123 8 fn7670.0 december 23, 2011 typical performance curves figure 3. HIP2122 i dd operating current vs fr equency figure 4. hip2123 i dd operating current vs frequency figure 5. i hb operating current vs frequency figure 6. i hbs operating current vs frequency figure 7. high level output voltag e vs temperature figure 8. low leve l output voltage vs temperature 0.1 1.0 10.0 frequency (hz) i ddo (ma) t = +25c t = +125c t = +150c 10k 100k 1m t = -40c 10k 100k 1m 0.1 1.0 10.0 frequency (hz) i ddo (ma) t = +25c t = -40c t = +125c t = +150c frequency (hz) i hbo ( m a) 0.01 1.0 10.0 t = +25c t = +125c t = +150c 10k 100k 1m 0.1 t = -40c frequency (hz) i hbso (ma) 0.01 1.0 10.0 t = +25c t = -40c t = +125c t = +150c 10k 100k 1m 0.1 -50 0 50 100 150 50 100 150 200 250 300 temperature (c) v ohl , v ohh (mv) v dd = v hb = 12v v dd = v hb = 14v v dd = v hb = 8v -50 0 50 100 150 50 100 150 200 v oll , v olh (mv) temperature (c) v dd = v hb = 12v v dd = v hb = 14v v dd = v hb = 8v
HIP2122, hip2123 9 fn7670.0 december 23, 2011 figure 9. undervoltage lockout threshold vs temperature figure 10. undervoltage lockout hysteresis vs temperature figure 11. HIP2122 propagation delays vs temperature figure 12. hip2123 propagation delays vs temperature figure 13. HIP2122 delay matching vs temperature f igure 14. hip2123 delay matching vs temperature typical performance curves (continued) v ddr , v hbr (v) -50 0 50 100 150 6.7 temperature (c) v hbr v ddr 6.5 6.3 6.1 5.9 5.7 5.5 5.3 v ddh , v hbh (v) 0.70 temperature (c) v hbh v ddh 0.65 0.60 0.55 0.50 0.45 0.40 -50 0 50 100 150 25 30 35 40 45 50 55 t lplh , t lphl , t hplh , t hphl (ns) temperature (c) t lphl t hphl t lplh t hplh -50 0 50 100 150 25 30 35 40 45 50 55 t lplh , t lphl , t hplh , t hphl (ns) temperature (c) t hplh t lplh t hphl t lphl -50 0 50 100 150 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 t mon , t moff ( ns ) temperature (c) t mon t moff -50 0 50 100 150 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 t mon , t moff (ns) temperature (c) t moff t mon -50 0 50 100 150
HIP2122, hip2123 10 fn7670.0 december 23, 2011 figure 15. peak pull-up current vs output voltage f igure 16. peak pull-down current vs output voltage figure 17. HIP2122 quiescent current vs voltage f igure 18. hip2123 quiescent current vs voltage figure 19. bootstrap diode i- v characteristics figure 20. v hs voltage vs v dd voltage typical performance curves (continued) 0481012 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v lo , v ho (v) i ohl , i ohh (a) 26 0481012 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v lo , v ho (v) i ohl , i ohh (a) 26 1.0 0.5 0 5 10 15 20 0 10 20 30 40 50 60 70 80 90 100 110 120 v dd , v hb (v) i dd , i hb (a) i hb i dd 0 5 10 15 20 v dd , v hb (v) i dd , i hb (a) 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 i dd i hb 0.3 0.4 0.5 0.6 0.7 0.8 1 . 10 -3 0.01 0.10 1.00 forward voltage (v) forward current (a) 1 . 10 -4 1 . 10 -5 1 . 10 -6 12 13 14 15 16 0 20 40 60 80 100 120 v hs to v ss voltage (v) v dd to v ss voltage (v)
HIP2122, hip2123 11 fn7670.0 december 23, 2011 functional description functional overview the HIP2122/23 have independent control inputs, li and hi, for each output; lo and ho. when li is low, lo is low and likewise, when hi is low, ho is low. the output negative transitions occur with minimal (and fixe d) propagation delays. the positive transitions of each output are delayed by the programmed delay as set by rdt. with 80k, the delay is nominally 25ns. with 8k, the delay is nominally 220ns. resistors values less than 8k and greater than 80k are not recommended. the delay time as a function of r dt is approximately t dt (ns) = 2/r dt . delaying the rising edge but not th e falling edge of each output is the technique that prevents shoot-thru. please note that there is no logic that prevents both outputs from being on if both inputs are on simultaneously. the enable pin, en, when low, drives both outputs to a low state. when the pwm input transitions, it is necessary to insure that both bridge fets are not on at the same time to prevent shoot-through currents (break be fore make). the programmable dead time forces both outputs to be off before either of the bridge fets is driven on. an 8k ? resistor connected between r dt and v ss results in a nominal dead time of 250ns. an 80k ? results with a minimum nominal dead time of 50ns. resistors values less than 8k and greater than 80k are not recommended. dead-time as a function of r dt is nominally t dt (ns) = 2/r dt . the high-side driver bias is established by the boot capacitor connected between hb and hs. the charge on the boot capacitor is provided by the internal boot diode that is connected to v dd . the current path to charge the boot capacitor occurs when the low-side bridge fet is on. this charge current is limited in amplitude by the inherent resistan ce of the boot diode and by the drain-source voltage of the low-si de fet. assuming that the on time of the low-side fet is sufficiently long to fully charge the boot capacitor, the boot voltage will charge very close to v dd (less the boot diode drop and the low-side fet on voltage). when the hi input transitions high, the high-side bridge fet is driven on after the delay time. because the hs node is connected to the source of the high-side fet, the hs node will rise almost to the level of the bridge voltage (less the conduction voltage across the bridge fet). because the boot capacitor voltage is referenced to the source voltage of the hi gh-side fet, the hb node is v dd volts above the hs node and the boot diode is reversed biased. because the high-side driver circuit is referenced to the hs node, the ho output is now approximately vhb + vbridge above ground. during the low to high transiti on of the hs node, the boot capacitor sources the necessary gate charge to fully enhance the high-side bridge fet gate. after the gate is fully charged, the boot capacitor no longer sources the charge to the gate but continues to provide bias current to the high-side driver. it is clear that the charge of the boot capacitor must be substantially larger than the required charge of the high -side fet and high-side driver otherwise the boot voltage will sag excessively. if the boot capacitor value is too small for the required maximum of on-time of the high-side fet, the high -side uv lockout may engage resulting with an unexpected operation. application information selecting the boot capacitor value the boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but also, and more significantly, to provide the gate charge of the driven fet without causing the boot voltage to sag excessively. in practice, the boot capacitor should have a total charge that is about 20 times the gate charge of the driven power fet for approximately a 5% drop in voltage after the charge has been transferred from the boot capacitor to the gate capacitance. the following parameters are required to calculate the value of the boot capacitor for a specific amount of voltage droop. in this example, the values used are arbi trary. they should be changed to comply with the actual application. the following equations calculate the total charge required for the period. this equation assumes that all of the parameters are constant during the period duration. the error is insignificant if the ripple is small. v dd = 10v v dd can be any value between 7 and 14vdc v hb = v dd - 0.6v = v ho high side driver bias voltage (v dd - boot diode voltage) referenced to v hs period = 1ms this is the longest expected switching period i hb = 100a worst case high side driver current when xho = high (this value is specified for v dd = 12v but the error is not significant) r gs = 100k ? gate-source resistor (usually not needed) ripple = 5% desired ripple voltage on the boot capacitor (larger ripple is not recommended) i gate_leak = 100na from the fet vendor?s datasheet qgate80v = 64nc from figure 21 figure 21. typical gate charge of a power fet 12 10 8 6 4 2 0 10 20 30 40 50 60 70 80 qg total gate charge (nc) vgs, gate-to-source voltage (v) 0 v ds = 80v v ds = 50v v ds = 20v i d = 33a
HIP2122, hip2123 12 fn7670.0 december 23, 2011 q c = q gate80v + period x (i hb + v ho /r gs + i gate_leak ) c boot = q c /(ripple * vdd) c boot = 0.52f if the gate to source resistor is removed (r gs is usually not needed or recommended), then: c boot = 0.33f typical application circuit figure 23 is an example of how the HIP2122/23 can be configured for a half bridge power supply application. depending on the application, th e switching speed of the bridge fets can be reduced by adding series connected resistors between the xho outputs and the fet gates. gate-source resistors are recommended on the low side fets to prevent unexpected turn-on of the bridge should the bridge voltage be applied before vdd. gate-source resistors on the high side fets are not usually required if low- side gate-source resistors are used. if relatively small gate-s ource resistors are used on the high-side fets, be aware that they will load the boot capacitor, which will then require a larger value for the boot capacitor. transients on hs node an important operating condition that is frequently overlooked by designers is the negative transient on the xhs pins that occurs when the high side bridge fet turns off. the absolute maximum transient allowed on the xhs pin is -6v but it is wise to minimize the amplitude to lower levels. this transient is the result of the parasitic inductance of the low-side drain-source conductor on the pcb. even the parasitic inductance of the low-side fet contributes to this transient. when the high-side bridge fet turns off (see figure 22), because of the inductive characteristics of the load, the current that was flowing in the high-side fet (blue) must rapidly commutate to flow through the low side fet (red). the amplitude of the negative transient impressed on the xhs node is (di/dt x l) where l is the total parasitic inductance of the low-side fet drain- source path and di/dt is the rate at which the high-side fet is turned off. with the increasing power levels of power supplies and motor, clamping this tran sient become more and more significant for the proper operation of the HIP2122/23. there are several ways of reducing the amplitude of this transient. if the bridge fets are turned off more slowly to reduce di/dt, the amplitude will be redu ced but at the expense of more switching losses in the fets. carefu l pcb design will also reduce the value of the parasitic inductance. however, these two solutions by themselves may no t be sufficient. figure 22 illustrates a simple me thod for clamping the negative transient. a fast pn junction, 1a diode is connected between xhs and vss as shown. it is important that this diode be placed as close as possible to the xhs and vss pins to minimize the parasitic inductance of this current path. because this clamping diode is essentially in parallel with the bo dy diode of the low side fet, a small value resistor is necessary to limit current when the body diode of the low side bridge fet is conducting during the dead time. please note that a similar transien t with a positive polarity occurs when the low-side fet turns off. this is less frequently a problem because xhs node is floating up toward the bridge bias voltage. the absolute max voltage rating for the xhs node does need to be observed when the positive transient occurs. vss hs lo ho inductive load + - + - figure 22. parasitic inductance causes transients on hs node isl78420 hi driver lo driver logic ho lo hs pwm en rdt vss vdd hb 8-15v 100v max pwm controller figure 23. typical half bridge application
HIP2122, hip2123 13 fn7670.0 december 23, 2011 power dissipation the dissipation of the HIP2122/ 23 is dominated by the gate charge required by the driven bridge fets and the switching frequency. the internal bias and b oot diode also contribute to the total dissipation but these losses are usually insignificant compared to the gate charge losses. the calculation of the power di ssipation of the HIP2122/23 is very simple. gate power (for the ho and lo outputs): p gate = 4 x q gate x freq x vdd where q gate is the charge of the driven bridge fet at vdd, and freq is the switching frequency. boot diode dissipation: i diode_avg = q gate x freq p diode = i diode_avg x 0.6v where 0.6v is the diode conduction voltage bias current: p bias = i bias x vdd where i bias is the internal bias curren t of the HIP2122/23 at the switching frequency total power dissipation: p total = p gate + p diode + p bias operating temperatures: t j = p total x ja + t amb where t j is the junction temperature at the operating air temperature, t amb , in the vicinity of the part. t j = p total x jc + t pcb where t j is the junction temperat ure with the operating temperature of the pcb, t pcb , measured where the epad is soldered. pc board layout the ac performance of the HIP2122/23 depends significantly on the design of the pc board. the following layout design guidelines are recommended to achieve optimum performance from the HIP2122/23: ? understand well how power curr ents flow. the high amplitude di/dt currents of the bridge fets will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they ?re usually more effective than parallel traces. ? planes can also be non-grounded nodes. ? avoid paralleling high di/dt traces with low level signal lines. high di/dt will induce currents in the low level signal lines. ? when practical, minimize impedances in low level signal circuits; the noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. ? be aware of magnetic fields em anating from transformers and inductors. core gaps in these st ructures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines. ? the use of low inductance components, such as chip resistors and chip capacitors is recommended. ? use decoupling capacitors to reduce the influence of parasitic inductors. to be effective, these capacitors must also have the shortest possible lead lengths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resi stance to dampen resonating parasitic circuits. the most likely circuit will be the ho and lo outputs. in pcb designs with long leads on the li and hi inputs, it may also be necessary to add series resistors with the li and hi inputs. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. this is especially true for the pwm control circuits. ? avoid having a signal ground pl ane under a high dv/dt circuit. this will inject high di/dt currents into the signal ground paths. ? do power dissipation and voltage drop calculations of the power traces. most pcb/cad prog rams have built in tools for calculation of trace resistance. ? large power components (power fets, electrolytic capacitors, power resistors, etc.) will have internal parasitic inductance, which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components. epad design considerations the thermal pad of the HIP2122/23 is electrically isolated. it?s primary function is to provide heat sinking for the ic. it is recommended to tie the epad to v ss (gnd). the following is an example of how to use vias to remove heat from the ic substrate.
HIP2122, hip2123 14 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7670.0 december 23, 2011 for additional products, see www.intersil.com/product_tree depending on the amount of power dissipated by the HIP2122/23, it may be necessary, to connect th e epad to one or more ground plane layers. a via array, within the area of the epad, will conduct heat from the epad to the gnd plane on the bottom layer. if inner pcb layers are available, it is also be desirable to connect these additional layers with the plated-through vias. the number of vias and the size of the gnd planes required for adequate heatsinking is determined by the power dissipated by the HIP2122/23, the air flow, and the maximum temperature of the air around the ic. it is important that the vias ha ve a low thermal resistance for efficient heat transfer. do not us e ?thermal relief? patterns to connect the vias. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: HIP2122, hip2123 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear figure 24. pcb via pattern epad gnd plane component layer epad gnd plane bottom layer figure 24. typical pcb pattern for thermal vias revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change december 23, 2011 fn7670.0 initial release
HIP2122, hip2123 15 fn7670.0 december 23, 2011 package outline drawing l9.4x4 9 lead thin dual flat no-lead plastic package rev 1, 1/10 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be e-pad is offset from center. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 4.00 2.20 0.15 (3.80) (4x) (9x 0.30) (6x 0.8) 0 .75 base plane c seating plane 0.08 c 0.10 c 9 x 0.30 see detail "x" 0.10 4 ca mb index area 6 pin 1 4.00 a b pin #1 index area bsc 3.2 ref 6x 0.80 6 (9 x 0.60) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 9x 0 . 40 0.100 3.00 (2.20) (3.00) 0.05 m c 5 4 9 1 1.2 ref 4 (1.2)
HIP2122, hip2123 16 fn7670.0 december 23, 2011 package outline drawing l10.4x4 10 lead thin dual flat no-lead plastic package rev 1, 1/08 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 4.00 2.60 0.15 ( 3.80) (4x) ( 10x 0 . 30 ) ( 8x 0 . 8 ) 0 .75 base plane c seating plane 0.08 c 0.10 c 10 x 0.30 see detail "x" 0.10 4 ca mb index area 6 pin 1 4.00 a b pin #1 index area bsc 3.2 ref 8x 0.80 6 ( 10 x 0.60 ) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 10x 0 . 40 3.00 ( 2.60) ( 3.00 ) 0.05 m c 6 5 10 1

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